Core8051
Timer/Counter Mode Control Register (tmod)
Table 22 displays the tmod register functions.
Table 22 ? tmod Register Flags
MSB
LSB
GATE
C/T
M1
M0
GATE
C/T
M1
M0
Timer 1
Timer 0
Table 23 provides tmod register bits descriptions.
Table 23 ? tmod Register Bits Description
Bit
Symbol Function
7,3
6, 2
5, 1
4, 0
GATE
C/T
M1
M0
If set, enables external gate control (pin int0 or int1 for Counter 0 or Counter 1, respectively). When int0 or int1
is high, and the trx bit is set (see tcon register), the counter is incremented every falling edge on the t0 or t1 input
pin.
Selects Timer or Counter operation. When set to logic 1, a Counter operation is performed. When cleared to
logic 0, the corresponding register will function as a Timer.
Selects the mode for Timer/Counter 0 or Timer/Counter 1.
Selects the mode for Timer/Counter 0 or Timer/Counter 1.
Table 24 provides timer and counter mode descriptions.
Table 24 ? Timers/Counter Mode Description
M1
0
M0
0
Mode
Mode 0
Function
13-bit Counter/Timer, with five lower bits in the tl0 or tl1 register and eight bits in the th0 or th1
register (for Timer 0 and Timer 1, respectively). The three high order bits of the tl0 and tl1 registers are
held at zero.
0
1
1
0
Mode 1
Mode2
16-bit Counter/Timer
8-bit auto-reload Counter/Timer. The reload value is kept in the th0 or th1 register, while the tl0 or tl1
register is incremented every machine cycle. When the tl0 or tl1 register overflows, the value in the th0
or th1 register is copied to the tl0 or tl1 register, respectively.
1
1
Mode3
If the M1 and M0 bits in Timer 1 are set to logic 1, Timer 1 stops. If the M1 and M0 bits in Timer 0 are
set to logic 1, Timer 0 acts as two independent 8-bit Timers/Counters.
Note: The th0 register is affected by the tr1 bit in the tcon register. When the th0 register overflows, the tf1 flag in the tcon register is set.
Timer/Counter Control Register (tcon)
Table 25 displays the tcon register flags.
Table 25 ? tcon Register Flags
MSB
LSB
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
v6.0
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